更新日：2024-12-02
以下、J-LinkコマンドラインツールからのRZ/T2HデバイスのメインCPU及びサブCPUへの同時接続方法を説明します。
CN60又はCN61コネクタにJ-Linkを接続してRZ/T2H EV-KIT評価ボードに電源を入れます。
J-Link Softwareパッケージの「J-Link Commander」ツールを起動します。「connect」コマンドを実行してRZ/T2Hデバイス（メインコア：Cortex-R52 CPU0）名「R9A09G077M44_R52_0」を指定します。ターゲットインターフェースモードにSWDを選択してメインCPU（R9A09G077M44_R52_0）に接続します。
SEGGER J-Link Commander V8.10i (Compiled Nov 27 2024 12:19:45) DLL version V8.10i, compiled Nov 27 2024 12:18:52 Connecting to J-Link via USB...O.K. Firmware: J-Link V12 compiled Oct 9 2024 10:52:31 Hardware version: V12.00 J-Link uptime (since boot): 0d 03h 51m 04s S/N: 60201xxxx License(s): RDI, FlashBP, FlashDL, JFlash, GDB USB speed mode: High speed (480 MBit/s) VTref=3.294V Type "connect" to establish a target connection, '?' for help J-Link>connect Please specify device / core.: R9A09G077M44_A55_0 Type '?' for selection dialog Device>R9A09G077M44_R52_0 Please specify target interface: J) JTAG (Default) S) SWD T) cJTAG TIF>S Specify target interface speed [kHz]. : 4000 kHz Speed> Device "R9A09G077M44_R52_0" selected. Connecting to target via SWD ConfigTargetSettings() start ConfigTargetSettings() end - Took 28us InitTarget() start Authenticated device detected. Skipping authentication process. OCDREG_STATUS: 0x00000001 InitTarget() end - Took 2.31ms Found SW-DP with ID 0x6BA02477 DPIDR: 0x6BA02477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[2]: AXI-AP (IDR: Not set, ADDR: 0x00000000) Using preconfigured AP[1] as APB-AP AP[1]: APB-AP found DebugRegs + CTI manually specified. ROM table scan skipped. Cortex-R52 @ 0x80410000 (configured) CoreCTI @ 0x80420000 (configured) Debug architecture: ARMv8.0 8 code breakpoints, 8 data breakpoints Processor features: EL0 support: AArch32 EL1 support: AArch32 EL2 support: AArch32 EL3 support: N/A FPU support: Single + Double + Conversion Add. info (CPU temp. halted) Current exception level: EL2 Exception level AArch usage: EL0: AArch32 EL1: AArch32 EL2: AArch32 EL3: AArch32 Non-secure status: Non-secure Cache info: Inner cache boundary: none LoU Uniprocessor: 1 LoC: 1 LoU Inner Shareable: 1 I-Cache L1: 16 KB, 64 Sets, 64 Bytes/Line, 4-Way D-Cache L1: 16 KB, 64 Sets, 64 Bytes/Line, 4-Way Memory zones: Zone: "Default" Description: Default access mode Zone: "AP0" Description: MEM-AP (APB-AP) Zone: "AP1" Description: MEM-AP (APB-AP) Zone: "AP2" Description: MEM-AP (AXI-AP) Cortex-R52 identified. J-Link>
「mem」コマンドでメモリ・I/Oレジスタのデータ読み出しを実行します。以下の事例では、内蔵SRAMの「0x10000000」アドレスにダミーデータ「0x12345678」を書き込みます。
J-Link>mem 0x40000000,40 Memory access: CPU temp. halted: https://wiki.segger.com/Memory_accesses#Legacy_stop_mode 40000000 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 40000010 = 00 00 00 00 4C 00 00 50 00 60 00 00 00 20 10 00 ....L..P.`... .. 40000020 = 00 00 00 00 00 00 00 00 FF FF FF 00 00 00 07 00 ................ 40000030 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ J-Link>w4 0x10000000, 0x12345678 Writing 12345678 -> 10000000 J-Link>mem32 0x10000000, 10 10000000 = 12345678 00000000 00000000 00000000 10000010 = 00000000 00000000 00000000 00000000 10000020 = 00000000 00000000 00000000 00000000 10000030 = 00000000 00000000 00000000 00000000 J-Link>
複数のJ-Link Commanderプログラムを同時に起動してRZ/T2HデバイスのメインCPU（Cortex-R52 CPU0）とサブCPUへの同時接続・メモリアクセスなど確認します。
※J-Link Commanderツール側の制限としてパソコンから同時に起動できるコマンドラインパネルは最大「5」までです。
Cortex-R52 CPU0へのJ-Link接続パネルをそのままで、新規「J-Link Commander」ツールを起動します。「connect」コマンドを実行してRZ/T2HデバイスのCortex-R52 CPU1コア（デバイス名：R9A09G077M44_R52_1）を指定します。ターゲットインターフェースモードにSWDを選択してサブCPU（Cortex-R52 CPU1）に接続します。接続後に内蔵SRAMの「0x10000000」アドレスのデータアクセスを確認します。
J-Link>connect Please specify device / core.: R9A09G077M44_R52_0 Type '?' for selection dialog Device>R9A09G077M44_R52_1 Please specify target interface: J) JTAG (Default) S) SWD T) cJTAG TIF>S Specify target interface speed [kHz]. : 4000 kHz Speed> Device "R9A09G077M44_R52_1" selected. Connecting to target via SWD ConfigTargetSettings() start ConfigTargetSettings() end - Took 23us InitTarget() start Releasing CPU1 from reset InitTarget() end - Took 7.55ms Found SW-DP with ID 0x6BA02477 DPIDR: 0x6BA02477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[2]: AXI-AP (IDR: Not set, ADDR: 0x00000000) Using preconfigured AP[1] as APB-AP AP[1]: APB-AP found DebugRegs + CTI manually specified. ROM table scan skipped. Cortex-R52 @ 0x80810000 (configured) CoreCTI @ 0x80820000 (configured) Debug architecture: ARMv8.0 8 code breakpoints, 8 data breakpoints Processor features: EL0 support: AArch32 EL1 support: AArch32 EL2 support: AArch32 EL3 support: N/A FPU support: Single + Double + Conversion Current exception level: EL2 Exception level AArch usage: EL0: AArch32 EL1: AArch32 EL2: AArch32 EL3: AArch32 Non-secure status: Non-secure Cache info: Inner cache boundary: none LoU Uniprocessor: 1 LoC: 1 LoU Inner Shareable: 1 I-Cache L1: 16 KB, 64 Sets, 64 Bytes/Line, 4-Way D-Cache L1: 16 KB, 64 Sets, 64 Bytes/Line, 4-Way Memory zones: Zone: "Default" Description: Default access mode Zone: "AP0" Description: MEM-AP (APB-AP) Zone: "AP1" Description: MEM-AP (APB-AP) Zone: "AP2" Description: MEM-AP (AXI-AP) Cortex-R52 identified. J-Link>mem32 0x10000000, 10 10000000 = 12345678 00000000 00000000 00000000 10000010 = 00000000 00000000 00000000 00000000 10000020 = 00000000 00000000 00000000 00000000 10000030 = 00000000 00000000 00000000 00000000 J-Link>
メインCPU（Cortex-R52 CPU0）へのJ-Link接続パネルをそのままで、新規「J-Link Commander」ツールを起動します。「connect」コマンドを実行してRZ/T2HデバイスのCortex-A55 CPU0コア（デバイス名：R9A09G077M44_A55_0）を指定します。ターゲットインターフェースモードにSWDを選択してサブCPU（Cortex-A55 CPU0）に接続します。接続後に内蔵SRAMの「0x10000000」アドレスのデータアクセスを確認します。
J-Link>connect Please specify device / core.: R9A09G077M44_R52_1 Type '?' for selection dialog Device>R9A09G077M44_A55_0 Please specify target interface: J) JTAG (Default) S) SWD T) cJTAG TIF>S Specify target interface speed [kHz]. : 4000 kHz Speed> Device "R9A09G077M44_A55_0" selected. Connecting to target via SWD ConfigTargetSettings() start ConfigTargetSettings() end - Took 23us InitTarget() start Authenticated device detected. Skipping authentication process. OCDREG_STATUS: 0x00000001 _SWR550_ADDR: 0x00000001 Releasing CA55_0 from reset Starting PLL0 InitTarget() end - Took 10.4ms Found SW-DP with ID 0x6BA02477 DPIDR: 0x6BA02477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[2]: AXI-AP (IDR: Not set, ADDR: 0x00000000) Using preconfigured AP[1] as APB-AP AP[1]: APB-AP found DebugRegs + CTI manually specified. ROM table scan skipped. Cortex-A55 @ 0x80C10000 (configured) CoreCTI @ 0x80C20000 (configured) Debug architecture: ARMv8.2 6 code breakpoints, 4 data breakpoints Processor features: EL0 support: AArch64 + AArch32 EL1 support: AArch64 + AArch32 EL2 support: AArch64 + AArch32 EL3 support: AArch64 + AArch32 FPU support: Single + Double + Conversion + single arithmetic Current exception level: EL3 Exception level AArch usage: EL0: AArch32 EL1: AArch32 EL2: AArch32 EL3: AArch64 Non-secure status: Secure Cache info: Inner cache boundary: L2 LoU Uniprocessor: 0 LoC: 2 LoU Inner Shareable: 0 I-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way Unified-Cache L2: 1024 KB, 1024 Sets, 64 Bytes/Line, 16-Way VMSAv8-64: Supports 48-bit VAs Memory zones: Zone: "Default" Description: Default access mode Zone: "AP0" Description: MEM-AP (APB-AP) Zone: "AP1" Description: MEM-AP (APB-AP) Zone: "AP2" Description: MEM-AP (AXI-AP) Cortex-A55 identified. J-Link>mem32 0x10000000, 4 10000000 = 12345678 00000000 00000000 00000000 J-Link>
メインCPU（Cortex-R52 CPU0）へのJ-Link接続パネルをそのままで、新規「J-Link Commander」ツールを起動します。「connect」コマンドを実行してRZ/T2HデバイスのCortex-A55 CPU1コア（デバイス名：R9A09G077M44_A55_1）を指定します。ターゲットインターフェースモードにSWDを選択してサブCPU（Cortex-A55 CPU1）に接続します。接続後に内蔵SRAMの「0x10000000」アドレスのデータアクセスを確認します。
J-Link>connect Please specify device / core.: R9A09G077M44_A55_0 Type '?' for selection dialog Device>R9A09G077M44_A55_1 Please specify target interface: J) JTAG (Default) S) SWD T) cJTAG TIF>S Specify target interface speed [kHz]. : 4000 kHz Speed> Device "R9A09G077M44_A55_1" selected. Connecting to target via SWD ConfigTargetSettings() start ConfigTargetSettings() end - Took 22us InitTarget() start Authenticated device detected. Skipping authentication process. OCDREG_STATUS: 0x00000001 Releasing CA55_1 from reset InitTarget() end - Took 6.43ms Found SW-DP with ID 0x6BA02477 DPIDR: 0x6BA02477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[2]: AXI-AP (IDR: Not set, ADDR: 0x00000000) Using preconfigured AP[1] as APB-AP AP[1]: APB-AP found DebugRegs + CTI manually specified. ROM table scan skipped. Cortex-A55 @ 0x80D10000 (configured) CoreCTI @ 0x80D20000 (configured) Debug architecture: ARMv8.2 6 code breakpoints, 4 data breakpoints Processor features: EL0 support: AArch64 + AArch32 EL1 support: AArch64 + AArch32 EL2 support: AArch64 + AArch32 EL3 support: AArch64 + AArch32 FPU support: Single + Double + Conversion + single arithmetic Current exception level: EL3 Exception level AArch usage: EL0: AArch32 EL1: AArch32 EL2: AArch32 EL3: AArch64 Non-secure status: Secure Cache info: Inner cache boundary: L2 LoU Uniprocessor: 0 LoC: 2 LoU Inner Shareable: 0 I-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way Unified-Cache L2: 1024 KB, 1024 Sets, 64 Bytes/Line, 16-Way VMSAv8-64: Supports 48-bit VAs Memory zones: Zone: "Default" Description: Default access mode Zone: "AP0" Description: MEM-AP (APB-AP) Zone: "AP1" Description: MEM-AP (APB-AP) Zone: "AP2" Description: MEM-AP (AXI-AP) Cortex-A55 identified. J-Link>mem32 0x10000000, 4 10000000 = 12345678 00000000 00000000 00000000 J-Link>
メインCPU（Cortex-R52 CPU0）へのJ-Link接続パネルをそのままで、新規「J-Link Commander」ツールを起動します。「connect」コマンドを実行してRZ/T2HデバイスのCortex-A55 CPU2コア（デバイス名：R9A09G077M44_A55_2）を指定します。ターゲットインターフェースモードにSWDを選択してサブCPU（Cortex-A55 CPU2）に接続します。接続後に内蔵SRAMの「0x10000000」アドレスのデータアクセスを確認します。
J-Link>connect Please specify device / core.: R9A09G077M44_A55_1 Type '?' for selection dialog Device>R9A09G077M44_A55_2 Please specify target interface: J) JTAG (Default) S) SWD T) cJTAG TIF>S Specify target interface speed [kHz]. : 4000 kHz Speed> Device "R9A09G077M44_A55_2" selected. Connecting to target via SWD ConfigTargetSettings() start ConfigTargetSettings() end - Took 22us InitTarget() start Authenticated device detected. Skipping authentication process. OCDREG_STATUS: 0x00000001 Releasing CA55_2 from reset InitTarget() end - Took 10.6ms Found SW-DP with ID 0x6BA02477 DPIDR: 0x6BA02477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[2]: AXI-AP (IDR: Not set, ADDR: 0x00000000) Using preconfigured AP[1] as APB-AP AP[1]: APB-AP found DebugRegs + CTI manually specified. ROM table scan skipped. Cortex-A55 @ 0x80E10000 (configured) CoreCTI @ 0x80E20000 (configured) Debug architecture: ARMv8.2 6 code breakpoints, 4 data breakpoints Processor features: EL0 support: AArch64 + AArch32 EL1 support: AArch64 + AArch32 EL2 support: AArch64 + AArch32 EL3 support: AArch64 + AArch32 FPU support: Single + Double + Conversion + single arithmetic Current exception level: EL3 Exception level AArch usage: EL0: AArch32 EL1: AArch32 EL2: AArch32 EL3: AArch64 Non-secure status: Secure Cache info: Inner cache boundary: L2 LoU Uniprocessor: 0 LoC: 2 LoU Inner Shareable: 0 I-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way Unified-Cache L2: 1024 KB, 1024 Sets, 64 Bytes/Line, 16-Way VMSAv8-64: Supports 48-bit VAs Memory zones: Zone: "Default" Description: Default access mode Zone: "AP0" Description: MEM-AP (APB-AP) Zone: "AP1" Description: MEM-AP (APB-AP) Zone: "AP2" Description: MEM-AP (AXI-AP) Cortex-A55 identified. J-Link>mem32 0x10000000, 4 10000000 = 12345678 00000000 00000000 00000000 J-Link>
メインCPU（Cortex-R52 CPU0）へのJ-Link接続パネルをそのままで、新規「J-Link Commander」ツールを起動します。「connect」コマンドを実行してRZ/T2HデバイスのCortex-A55 CPU3コア（デバイス名：R9A09G077M44_A55_3）を指定します。ターゲットインターフェースモードにSWDを選択してサブCPU（Cortex-A55 CPU3）に接続します。接続後に内蔵SRAMの「0x10000000」アドレスのデータアクセスを確認します。
J-Link>connect Please specify device / core.: R9A09G077M44_A55_2 Type '?' for selection dialog Device>R9A09G077M44_A55_3 Please specify target interface: J) JTAG (Default) S) SWD T) cJTAG TIF>S Specify target interface speed [kHz]. : 4000 kHz Speed> Device "R9A09G077M44_A55_3" selected. Connecting to target via SWD ConfigTargetSettings() start ConfigTargetSettings() end - Took 21us InitTarget() start Authenticated device detected. Skipping authentication process. OCDREG_STATUS: 0x00000001 Releasing CA55_3 from reset InitTarget() end - Took 7.91ms Found SW-DP with ID 0x6BA02477 DPIDR: 0x6BA02477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000) AP[2]: AXI-AP (IDR: Not set, ADDR: 0x00000000) Using preconfigured AP[1] as APB-AP AP[1]: APB-AP found DebugRegs + CTI manually specified. ROM table scan skipped. Cortex-A55 @ 0x80F10000 (configured) CoreCTI @ 0x80F20000 (configured) Debug architecture: ARMv8.2 6 code breakpoints, 4 data breakpoints Processor features: EL0 support: AArch64 + AArch32 EL1 support: AArch64 + AArch32 EL2 support: AArch64 + AArch32 EL3 support: AArch64 + AArch32 FPU support: Single + Double + Conversion + single arithmetic Current exception level: EL3 Exception level AArch usage: EL0: AArch32 EL1: AArch32 EL2: AArch32 EL3: AArch64 Non-secure status: Secure Cache info: Inner cache boundary: L2 LoU Uniprocessor: 0 LoC: 2 LoU Inner Shareable: 0 I-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way Unified-Cache L2: 1024 KB, 1024 Sets, 64 Bytes/Line, 16-Way VMSAv8-64: Supports 48-bit VAs Memory zones: Zone: "Default" Description: Default access mode Zone: "AP0" Description: MEM-AP (APB-AP) Zone: "AP1" Description: MEM-AP (APB-AP) Zone: "AP2" Description: MEM-AP (AXI-AP) Cortex-A55 identified. J-Link>mem32 0x10000000, 4 10000000 = 12345678 00000000 00000000 00000000 J-Link>mem 0x40000000, 40 40000000 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 40000010 = 00 00 00 00 4C 00 00 50 00 60 00 00 00 20 10 00 ....L..P.`... .. 40000020 = 00 00 00 00 00 00 00 00 FF FF FF 00 00 00 07 00 ................ 40000030 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ J-Link>
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